Characterization of the Deep Interface Traps in Hf-based/Si Gate Stacks

As continual complementary metal?oxide?semiconductor (CMOS) scaling requirements, metal gate/high-k dielectric/Si gate stacks are expected to replace poly-Si/SiO2/Si gate stacks in the future CMOS sub-45 nm technology node. Hafnium based oxide is a promising candidate to replace SiO2 as a gate dielectric, due to its much higher dielectric constant (high-k) and stability. The key challenges of successfully adopting the high-k dielectric/Si gate stack into advanced CMOS technology mostly come from the interfacial properties. The origins of the electrical and physical characteristics of the dielectric oxide/bulk interface were studied in detail. The leakage current density-voltage (J-V) and capacitance-voltage (C-V) measurement techniques were employed to study the dielectric oxide/Si interface. The effects of the post-deposition annealing (PDA) treatment on the interface charges of dielectric oxides were studied. We found that the PDA can effectively reduce the trapping density and leakage current, and eliminate hysteresis in the C?V curves. Besides, the changes in chemical bonding features at HfO2/Si, HfSiO/Si and HfSiON/Si interfaces due to PDA treatment were evaluated by XPS measurements. The XPS analysis provides a better interpretation of the electrical outcomes. As a result, both HfSiO and HfSiON films have exhibited superior performance in terms of thermal stability and electrical characteristics.