Part III – March 1969 - Papers- Solid-State Image Scanning Array

A silicon solid-state array image scanner is described. This paper deals with structural and performance properties of the array which basically consists of PIN photo and gating diodes, and low capacitance isolation diodes. Each chip of the array is composed of an 8 by 9 matrix of photo detector cells; each cell contains one each of the three diode types mentioned. This x-y matrix is read a column at a time with an access delay of approximately 100 nsec per column. It is designed to detect the presence or absence of illumination within 10-mil diam image spots located on a 15- by 15-mil grid. Radiant power level of an illuminated spot is low; of interest is the range around I uw with a of 8400g Structural improvements to the original array which will result THE purpose of this paper is to describe the results of a solid state scanner exploratory development activity. The scanner is intended to sense the presence or absence of low-level illumination falling upon a matrix of 10-mil wide squares arranged on a 15- by 15-mil x-y grid pattern. The light of interest has a wavelength of 8400, characteristic of radiation emitted from a GaAs lasing diode. This wavelength matches well the spectral absorption of silicon,' thus the well-developed silicon processing technology can be applied to fabricating large integrated arrays of PIN photocells to sense the radiation. The illumination state of the cells of the array is read, one column at a time, by addressing a drive line of the particular column in question and examining the state of those sense lines which are orthogonal to the drive Lines of in greater sensitivity at various wavelengths, both above and below 8400Å, and in greater speed are presented. These include variations in diffusion depth, resistivity of N and P regions, isolation techniques, and packaging. Trade-offs between access speed, cycle frequency, and sensitivity are discussed. A packaging approach to achieving an array composed of several chips is described. Requirements on this package are: 1) maintenance of 15- by 15-mil pitch of the light sensitive cell position, therefore positional accuracy of mounted 8 by 9 cell photo detector chips; 2) maintenance of inherent high array speed even though signal levels are low through high density close proximity mounting of monolithic sense amplifier circuitry. the array. One bank of N sense amplifiers is required, where N is the number of photodiode cells in each column of the array. CELL AND CHI" STRUCTURE A photograph of a single monolithic cell is shown in Fig. 1. Each cell is composed of three junctions, an isolation junction, a logic or blocking diode junction, and a photodiode junction; all of these junctions are connected electrically by a common N region. An electrical schematic of four cells of the array is shown in Fig. 2 with the associated driver and sense amplifier circuits in block diagram form. Note the common cathode configuration of the three diodes of each cell. Fig. 3, a diagram of the cell vertical struc ture, illustrates how the electrical configuration of